Article published Image processing
A high- definition video processor
Developed for mobile phones, eISP is one of the most competitive video processors on the market. Fully programmable, its new computing architecture may also have much to offer on other markets.
In addition to mobile phones, USB keys, MP3 players and PDAs are now equipped with CMOS video sensors, whose resolution is rapidly improving. In these highly competitive markets, cost control means reducing pixel size in the photosensitive matrix to allow higher resolution while maintaining a small silicon surface area. This leads to poorer image quality, which must be restored by combining noise reduction and colour recovery processing. This job is done by video processors, with very limited energy availability of a few hundred milliwatts (mW). Until now, dedicated processors were developed for the image processing algorithms of each generation of sensors. But this makes it impossible to integrate new algorithms during the product's lifecycle. "To overcome this lack of flexibility, we designed a programmable computing architecture with a minimum silicon footprint, which we call eISP, for embedded image signal processor,” explained Laurent Letellier, leader of the embedded calculations team at CEA LIST. "Although we made it using existing image processing algorithms, the resulting architecture will support the high-definition video (1900x1080 pixels) of tomorrow's mobile phones."
Military applications planned
The hardware architecture is based on a set of computing "tiles" comprising 2 to 16 processors depending on the desired configuration. It has a dataflow design, operating without one-shot memory, to reduce power consumption and surface area. The processors of a given tile work in parallel, in SIMD (single instruction multiple data) mode, making it possible to run the same code on several pixels at once using a single control unit. Specifically, a six-tile architecture with six processors per tile delivers 14 GOPS (billions of operations per second) at 200 MHz, for around 250 mW of power consumption. It occupies 1.3 mm2 of surface area (with the future 65-nm silicon etching technology). "This solution, which we patented in September 2008, is also easy to program,” noted Letellier. "The programmer focuses exclusively on the computing part and develops code for a single processor without worrying about parallelism or data access." This type of technology could also be used for the night vision equipment or digital binoculars used in military applications. "We are open to partnerships for both image-intensified and infrared vision applications,” added the researcher.
